The book "Time-to-Digital Converter dedicated to Dividerless ADPLL applications" offers a comprehensive analysis of a novel time-to-digital converter (TDC) specifically designed for All-Digital Phase-Locked Loop (ADPLL) applications. It highlights the TDC's ability to achieve high linearity and a wide input range with a normalized fractional output code. The presented topology is based on startable pseudo-differential delay cells and utilizes a Gated Ring Oscillator (GRO) format to extend the measurement time intervals. A special normalization unit has been developed to calibrate the output and measure phase errors for dividerless ADPLL applications. The book discusses various innovative approaches, including an improved variable phase accumulator and a high-resolution TDC with a resolution of less than 10 ps, suitable for a wide range of RF applications. The authors, including Sehmi Saad and Aymen Ben Hammadi, contribute their expertise in this specialized field.